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题名A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications
作者
发表日期2024-03-12
发表期刊IACR Transactions on Cryptographic Hardware and Embedded Systems
卷号2024期号:2页码:130-153
摘要

Lattice-Based Cryptography (LBC) schemes, like CRYSTALS-Kyber and CRYSTALS-Dilithium, have been selected to be standardized in the NIST Post-Quantum Cryptography standard. However, implementing these schemes in resource-constrained Internet-of-Things (IoT) devices is challenging, considering efficiency, power consumption, area overhead, and flexibility to support various operations and parameter settings. Some existing ASIC designs that prioritize lower power and area can not achieve optimal performance efficiency, which are not practical for battery-powered devices. Custom hardware accelerators in prior co-processor and processor designs have limited applications and flexibility, incurring significant area and power overheads for IoT devices. To address these challenges, this paper presents an efficient lattice-based cryptography processor with customized Single-Instruction-Multiple-Data (SIMD) instruction. First, our proposed SIMD architecture supports efficient parallel execution of various polynomial operations in 256-bit mode and acceleration of Keccak in 320-bit mode, both utilizing efficiently reused resources. Additionally, we introduce data shuffling hardware units to resolve data dependencies within SIMD data. To further enhance performance, we design a dual-issue path for memory accesses and corresponding software design methodologies to reduce the impact of data load/store blocking. Through a hardware/software co-design approach, our proposed processor achieves high efficiency in supporting all operations in lattice-based cryptography schemes. Evaluations of Kyber and Dilithium show our proposed processor achieves over 10× speedup compared with the baseline RISC-V processor and over 5× speedup versus ARM Cortex M4 implementations, making it a promising solution for securing IoT communications and storage. Moreover, Silicon synthesis results show our design can run at 200 MHz with 2.01 mW for Kyber KEM 512 and 2.13 mW for Dilithium 2, which outperforms state-of-the-art works in terms of PPAP (Performance × Power × Area).

关键词Internet-of-Things Lattice-Based Cryptography Post-quantum Cryptography RISC-V Single-Instruction-Multiple-Data
DOI10.46586/tches.v2024.i2.130-153
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语种英语English
Scopus入藏号2-s2.0-85187795395
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文献类型期刊论文
条目标识符https://repository.uic.edu.cn/handle/39GCC9TT/11484
专题理工科技学院
作者单位
1.Zhejiang University,Hangzhou,China
2.BNU-HKBU United International College,Zhuhai,China
3.City University of Hong Kong,Hong Kong
推荐引用方式
GB/T 7714
Ye, Zewen,Song, Ruibing,Zhang, Haoet al. A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024, 2024(2): 130-153.
APA Ye, Zewen, Song, Ruibing, Zhang, Hao, Chen, Donglong, Cheung, Ray Chak Chung, & Huang, Kejie. (2024). A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024(2), 130-153.
MLA Ye, Zewen,et al."A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications". IACR Transactions on Cryptographic Hardware and Embedded Systems 2024.2(2024): 130-153.
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