题名 | A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection |
作者 | |
发表日期 | 2022 |
会议名称 | 2022 IEEE Smartworld, Ubiquitous Intelligence & Computing, Scalable Computing & Communications, Digital Twin, Privacy Computing, Metaverse, Autonomous & Trusted Vehicles (SmartWorld/UIC/ScalCom/DigitalTwin/PriComp/Meta) |
会议录名称 | Proceedings - 2022 IEEE Smartworld, Ubiquitous Intelligence & Computing, Scalable Computing & Communications, Digital Twin, Privacy Computing, Metaverse, Autonomous & Trusted Vehicles (SmartWorld/UIC/ScalCom/DigitalTwin/PriComp/Meta)
![]() |
ISBN | 979-8-3503-4655-8 |
页码 | 540-549 |
会议日期 | 15-18 December 2022 |
会议地点 | Haikou, China |
出版者 | IEEE |
摘要 | Detecting and extracting textual information from natural scene images needs Scene Text Detection (STD) algorithms. Fully Convolutional Neural Networks (FCNs) are usually utilized as the backbone model to extract features in these instance segmentation based STD algorithms. FCNs naturally come with high computational complexity. Furthermore, to keep up with the growing variety of models, flexible architectures are needed. In order to accelerate various STD algorithms efficiently, a versatility-performance balanced hardware architecture is proposed, together with a simple but efficient way of configuration. This architecture is able to compute different FCN models without hardware redesign. The optimization is focused on hardware with finely designed computing modules, while the versatility of different network reconfigurations is achieved by microcodes instead of a strenuously designed compiler. Multiple parallel techniques at different levels and several complexity-reduction methods are explored to speed up the FCN computation. Results from implementation show that, given the same tasks, the proposed system achieves a better throughput compared with the studied GPU. Particularly, our system reduces the comprehensive Operation Expense (OpEx) at GPU by 46%, while the power efficiency is enhanced by 32%. This work has been deployed in commercial applications and provided stable consumer text detection services. |
关键词 | Filed-Programmable-Gate-Array (FPGA) Fully Convolutional Neural Network (FCN) Hardware Acceleration Instance Segmentation Scene Text Detection (STD) |
DOI | 10.1109/SmartWorld-UIC-ATC-ScalCom-DigitalTwin-PriComp-Metaverse56740.2022.00093 |
URL | 查看来源 |
语种 | 英语English |
Scopus入藏号 | 2-s2.0-85168156335 |
引用统计 | |
文献类型 | 会议论文 |
条目标识符 | https://repository.uic.edu.cn/handle/39GCC9TT/11675 |
专题 | 理工科技学院 |
通讯作者 | Chen, Donglong |
作者单位 | 1.Peng Cheng Laboratory,Shenzhen,China 2.National University of Defense Technology,Changsha,China 3.BNU-HKBU United International College,Zhuhai,China 4.Southern University of Science and Technology,Shenzhen,China 5.City University of Hong Kong,Hong Kong, China 6.Uc,Santa Barbara,United States 7.NUAA,China 8.Iǧdir University,Turkey |
通讯作者单位 | 北师香港浸会大学 |
推荐引用方式 GB/T 7714 | Xin, Yao,Tang, Guoming,Chen, Donglonget al. A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection[C]: IEEE, 2022: 540-549. |
条目包含的文件 | 条目无相关文件。 |
除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。
修改评论