科研成果详情

In this paper, we explore and analyse a heuristic mapping algorithm optimized for big data applications. Data are generated much faster nowadays. Multicore processors are widely used to process huge amount of data. It is expected that tens of even hundreds of cores will be integrated on a single processor. However, traditional mapping algorithm has not been well designed for big data applications. We investigate the behaviour of these applications. The on-chip traffic of an application is analysed in terms of cache and memory latencies. We propose a mapping algorithm for big data applications. The algorithm is optimized to reduce latencies to shared cache and memory controller, while inter-process communication is considered as well. To reduce search space, we propose calculating the mapping region with the congregate degree of nodes, together with an adjacent-contiguous-nearest expanding strategy. The mapping algorithm is compared with two other algorithms with several big data workloads. Experimental results show that, the overall system efficiency of the proposed algorithm has improved for 45.5% and 38.4% respectively, compared with other works.