Details of Research Outputs

In this paper, we propose a three dimensional storage-on-chip design that provides systems with high integration. The main memory and disk storage are stacked on-chip with through silicon vias. We analyse implementation feasibility, a 3D chip with multiple layers of DRAM and NAND storage is modelled accordingly. We use a sophisticated simulation toolset to analyse the performance of various architectures. Full system evaluation using SPLASH-2 benchmarks shows that, compared to conventional off-chip main memory and disk storage, our design can reduce the overall execution time by 38.3% on average. © 2013 ACM.