Details of Research Outputs

The Network-on-Chip (NoC) paradigm plays an essential role in designing emerging multicore processors. Three Dimensional (3D) NoC design expands the on-chip network vertically. To achieve high performance in a 3D NoC, it is crucial to reduce the access latency of caches and memories. In this paper, we propose an optimized design that provides high performance, low power consumption and manufacturing cost. The proposed scheme shifts the fully connected mesh network to a partially connected network, with the optimization of heterogeneous routers and links. Full system evaluation shows that, compared to a previous optimized heterogeneous design, OPTNOC can further reduce the execution time by 12.1% and energy delay product by 23.5%. © 2013 Springer-Verlag Berlin Heidelberg.