×
Verification Code:
换一张
Forgotten Password?
Stay signed in
×
Login
中文
|
English
BNBU
|
Library
Login
Register
Home
Publications
Faculty/School
Scholars
Analysis
Search
ALL
ORCID
Title
Creator
Date Issued
Keyword
Document Type
Original Document Type
Indexed By
Publisher
Status
Collection
Research outside affiliated...
1
Authors
JIA Weijia
1
Document Type
Conference paper
1
Journal article
1
Date Issued
2022
1
2008
1
Language
英语English
2
Indexed By
CPCI-S
1
SCIE
1
Funding Organization
Keyword
Memory management
2
Cryptography
1
Design automation
1
Merging
1
NIST
1
NTT
1
More...
Source Publication
ICASSP, IEEE International ...
1
IEEE Transactions on Comput...
1
Funding Project
×
Knowledge Map
Feedback
Browse/Search Results: 1-2 of 2
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Journal Impact Factor Ascending
Journal Impact Factor Descending
Submit date Ascending
Submit date Descending
Author Ascending
Author Descending
Issue Date Ascending
Issue Date Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Title Ascending
Title Descending
Time-memory Trade-offs for Saber+ on Memory-constrained RISC-V Platform
Journal article
IEEE Transactions on Computers,2022, volume: 71, issue: 11, pages: 2996-3007
Authors:
Zhang, Jipeng
;
Huang, Junhao
;
Liu, Zhe
;
Sinha Roy, Sujoy
Favorite
  |  
View/Download:5/0
  |  
Submit date:2022/02/23
Cryptography
lattice-based cryptography
Memory management
memory optimizations
Merging
NIST
NTT
Optimization
post-quantum cryptography
RISC-V
Saber
Transforms
Wireless sensor networks
Address Assignment Sensitive Variable Partitioning and scheduling for DSPS with multiple memory banks
Conference paper
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, Las Vegas, NV, USA, MAR 30-APR 04, 2008
Authors:
Xue, Chun Jason
;
Liu, Tiantian
;
Shao, Zili
;
Hu, Jingtong
;
Jia, Zhiping
Favorite
  |  
View/Download:3/0
  |  
Submit date:2021/07/30
Design automation
Memory management
Program compilers
Scheduling