×
Verification Code:
换一张
Forgotten Password?
Stay signed in
×
Login
中文
|
English
BNBU
|
Library
Login
Register
Home
Publications
Faculty/School
Scholars
Analysis
Search
ALL
ORCID
Title
Creator
Date Issued
Keyword
Document Type
Original Document Type
Indexed By
Publisher
Status
Collection
Research outside affiliate...
33
Authors
XU Thomas Canhao
32
Document Type
Conference paper
26
Journal article
6
Book chapter
1
Date Issued
2016
1
2015
2
2014
2
2013
5
2012
8
2011
9
More...
Language
英语English
33
Indexed By
CPCI-S
10
SCIE
3
Funding Organization
Keyword
Network-on-Chip
8
Multicore
6
Network-on-chip
5
Chip multiprocessor
4
multicore
3
network-on-chip
3
More...
Source Publication
Lecture Notes in Computer S...
5
ACM International Conferenc...
4
Journal of Systems Architec...
2
2009 NORCHIP
1
2011 NORCHIP
1
23th International Conferen...
1
More...
Funding Project
×
Knowledge Map
Feedback
Browse/Search Results: 1-10 of 33
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Journal Impact Factor Ascending
Journal Impact Factor Descending
Submit date Ascending
Submit date Descending
Author Ascending
Author Descending
Issue Date Ascending
Issue Date Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Title Ascending
Title Descending
On parallel online learning for adaptive embedded systems
Book chapter
出自: Artificial Intelligence: Concepts, Methodologies, Tools, and Applications, USA:IGI Global, 2016, pages: 1818-1839
Authors:
Pahikkala, Tapio
;
Liljeberg, Pasi
;
Airola, Antti
;
Tenhunen, Hannu
;
Xu, Thomas Canhao
Favorite
  |  
View/Download:3/0
  |  
Submit date:2022/06/13
Trio: A triple class on-chip network design for efficient multicore processors
Conference paper
Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015, New York, AUG 24-26, 2016
Authors:
Xu, Thomas Canhao
;
Leppänen, Ville
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
Cache
Design
Efficient
Multicore
Network-on-chip
PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems
Journal article
Concurrency and Computation: Practice and Experience,2015, volume: 27, issue: 4, pages: 1054-1067
Authors:
Xu, Thomas Canhao
;
Leppänen, Ville
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
efficiency
heterogeneous
hybrid
interconnect
multicore
network-on-chip
PDNOC: An efficient partially diagonal network-on-chip design
Conference paper
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Warsaw, SEP 08-11, 2013
Authors:
Xu, Thomas Canhao
;
Leppänen, Ville
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
3D Chip
Heterogeneous
Multicore
Network-on-Chip
Mixed-criticality run-time task mapping for NoC-based many-core systems
Conference paper
Proceedings - 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014, Turin, FEB 12-14, 2014
Authors:
Fattah, Mohammad
;
Rahmani, Amir Mohammad
;
Xu, Thomas Canhao
;
Kanduri, Anil
;
Liljeberg, Pasi
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
Application Mapping
Contiguous Task Mapping
Dynamic Many-Core Systems
Processor allocation
Evaluate and optimize parallel Barnes-Hut algorithm for emerging many-core architectures
Conference paper
Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, Helsinki, July 1-5, 2013
Authors:
Xu, Thomas Canhao
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
Barnes-Hut
Interconnection
Many-core
Mapping
Network-on-Chip
Parallel System
OPTNOC: An optimized 3D network-on-chip design for fast memory access
Conference paper
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Kaliningrad, 30 September 2013 到 4 October 2013
Authors:
Xu, Thomas Canhao
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
Optimized multicore architectures for data parallel fast Fourier transform
Conference paper
ACM International Conference Proceeding Series, Xi'an, June 28-29, 2013
Authors:
Xu, Thomas Canhao
;
Pahikkala, Tapio
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
data parallel
FFT
multicore
network-on-chip
optimization
MMSoC: A multi-layer multi-core storage-on-chip design for systems with high integration
Conference paper
ACM International Conference Proceeding Series, Bulgaria, June 28-29, 2013
Authors:
Xu, Thomas Canhao
;
Liljeberg, Pasi
;
Plosila, Juha
;
Tenhunen, Hannu
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
3D chip
memory
multi-core
network-on-chip
solid state disk
Optimal placement of vertical connections in 3D network-on-chip
Journal article
Journal of Systems Architecture,2013, volume: 59, issue: 7, pages: 441-454
Authors:
Xu, Thomas Canhao
;
Schley, Gert
;
Liljeberg, Pasi
;
Radetzki, Martin
;
Plosila, Juha
Favorite
  |  
View/Download:2/0
  |  
Submit date:2022/06/13
3D integration
Chip multiprocessor
Network-on-chip
Resource placement
Through silicon via