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PDNOC: An efficient partially diagonal network-on-chip design Conference paper
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Warsaw, SEP 08-11, 2013
Authors:  Xu, Thomas Canhao;  Leppänen, Ville;  Liljeberg, Pasi;  Plosila, Juha;  Tenhunen, Hannu
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MMSoC: A multi-layer multi-core storage-on-chip design for systems with high integration Conference paper
ACM International Conference Proceeding Series, Bulgaria, June 28-29, 2013
Authors:  Xu, Thomas Canhao;  Liljeberg, Pasi;  Plosila, Juha;  Tenhunen, Hannu
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Optimal placement of vertical connections in 3D network-on-chip Journal article
Journal of Systems Architecture,2013, volume: 59, issue: 7, pages: 441-454
Authors:  Xu, Thomas Canhao;  Schley, Gert;  Liljeberg, Pasi;  Radetzki, Martin;  Plosila, Juha
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A high-efficiency low-cost heterogeneous 3D network-on-chip design Conference paper
ACM International Conference Proceeding Series, Vancouver, 1 December 2012
Authors:  Xu, Thomas Canhao;  Liljeberg, Pasi;  Plosila, Juha;  Tenhunen, Hannu
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Exploring DRAM Last Level Cache for 3D Network-on-Chip architecture Conference paper
Advanced Materials Research, Kuala Lumpur, NOV 04-06, 2011
Authors:  Xu, Thomas Canhao;  Liljeberg, Pasi;  Tenhunen, Hannu
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A study of 3D Network-on-Chip design for data parallel H.264 coding Journal article
Microprocessors and Microsystems,2011, volume: 35, issue: 7, pages: 603-612
Authors:  Xu, Thomas Canhao;  Yin, Alexander Wei;  Liljeberg, Pasi;  Tenhunen, Hannu
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3D Network-on-Chip with on-chip DRAM: An empirical analysis for future Chip Multiprocessor Journal article
World Academy of Science, Engineering and Technology,2010, volume: 46, pages: 18-24
Authors:  Xu, Thomas Canhao;  Yang, Bo;  Yin, Alexander Wei;  Liljeberg, Pasi;  Tenhunen, Hannu
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